1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming FinFET devices with a shared gate structure.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
One problem encountered in manufacturing FinFET devices will now be described with reference to FIGS. 1A-1F. FIG. 1A is a perspective view of an illustrative FinFET semiconductor device 10 that is formed above a semiconducting substrate 12. The device 10 includes a plurality of fins 14, a gate electrode 13, sidewall spacers 17 and a gate cap layer 15. FIG. 1A depicts the locations where various cross-sectional views of the device 10 will be taken in the drawings discussed below. More specifically, view “X-X” is a cross-sectional view taken through the gate electrode 13 in a direction that is parallel to the long axis of the gate electrode 13, i.e., in the gate width direction, and view “Y-Y” is a cross-sectional view taken through the fins 14 in a direction that is transverse to the long axis of the fins 14. It should be understood that FIG. 1A is only provided to show the location of the various cross-sectional views depicted in the drawings below, and many aspects discussed below are not depicted in FIG. 1A so as to not overly complicate the device 10 depicted in FIG. 1A. Moreover, the reference numbers employed below for various structures may not match the reference numbers depicted in FIG. 1A.
FIGS. 1B-1F depict the illustrative situation where an N-type FinFET device will be formed adjacent to a P-type FinFET device, such as in an SRAM structure, and where the two devices will ultimately share a common gate structure. The N-type FinFET device is separated from the P-type FinFET device by an illustrative shallow trench isolation region 14 that is formed in the substrate 12. Illustrative STI regions 16 are also depicted. In the depicted example, the common gate structure for both devices will be formed using a so-called “replacement gate” or “gate last” technique. At the point of fabrication depicted in FIG. 1B, a plurality of fins 18N have been formed for the N-type FinFET device and a single fin 18P has been formed for the P-type FinFET device. The fins were formed by performing an etching process, such as a dry or wet etching process, through a patterned mask layer (not shown) to form a plurality of trenches 13 in the substrate 12 to thereby define the fins 18N, 18P. Also depicted in FIG. 1B is a sacrificial gate structure that is comprised of a sacrificial gate insulation layer 20, a sacrificial gate electrode 22 and a gate cap layer 24. A layer of sidewall spacer material 26 is also depicted in FIG. 1B. Such layers may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sacrificial gate insulation layer 20 may be comprised of silicon dioxide, the sacrificial gate electrode layer 22 may be comprised of polysilicon or amorphous silicon, and the gate cap layer 24 may be comprised of silicon nitride. The layers of material depicted in FIG. 1B may be formed by any of a variety of different known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, etc. The sacrificial gate structure may be formed by patterning the layers of material using traditional photolithography and etching processes. The gate cap layer 24 is typically relatively thick, e.g., about 60-100 nm, due to the etching processes it must withstand as the device is being fabricated, as discussed more fully below. The layer of sidewall spacer material 26 may have a thickness of about 10 nm and it may be comprised of materials such as silicon nitride, silicon oxynitride, silicon nitride carbon, etc.
FIG. 1C depicts the device after several process operations have been performed. First, a patterned etch mask 30N, e.g., a patterned photoresist mask, was formed on the device 10 so as to cover the N-type FinFET device and expose the P-type FinFET device for further processing. The patterned etch mask 30N has an edge 30NE. Thereafter, an anisotropic etching process operation was performed on the layer of sidewall spacer material 26 to thereby define a first sidewall spacer 26SP that is positioned on a first, exposed portion of the sacrificial gate structure and on the exposed fin 18P. Note that the first sidewall spacer 26SP extends around less than the entire perimeter of the sacrificial gate structure due to the presence of the mask layer 30N. One process operation that is commonly employed to form the first spacer 26SP involves performing an initial “main etch” that is non-selective in nature, and thus faster, to remove most of the thickness of the layer of spacer material 26. At some point, the main etch process is stopped and a selective “over-etch” process is performed to finish the removal of the layer of spacer material 26 and thereby define the first spacer 26SP. Importantly, the over-etch process is performed for a sufficient duration such that the fin 18P is cleared of any spacer material, as shown in FIG. 1C (view Y-Y). The exposed portion of the gate cap layer 24 is also etched or “gouged” during the formation of the spacer 26SP, as reflected by the recessed surface 24R. In some cases, as much as half of the original thickness of the gate cap layer 24 may be consumed during this process.
FIG. 1D depicts the device after several process operations have been performed. First, the masking layer 30N was removed and an epi pre-clean process was performed on the fin 18P to insure that the fin 18P is cleared of all materials that may be detrimental to the formation of an epi semiconductor material on the fin 18P, such as oxide materials, photoresist materials, etc. The epi pre-clean is typically performed using a dilute HF acid. The pre-clean process may consume a small amount of the STI region 14 and the STI region 16, but such consumption is not depicted in the drawings. After the pre-clean process was performed, an epi deposition process was performed to form a semiconductor material 32 on the fin 18P. The diamond-shaped nature of the semiconductor material 32 is due to the crystalline structure of the substrate material. Dashed line 34 depicts the outline of the original fin 18P. Thereafter, a very thin protection layer 36, e.g., 3-4 nm of silicon nitride, was conformably deposited on the device 10 so as to protect the fin 18P.
FIG. 1E depicts the device after several process operations have been performed. First, a patterned etch mask 30P, e.g., a patterned photoresist mask, was formed on the device 10 so as to cover the P-type FinFET device and expose the N-type FinFET device for further processing. The patterned etch mask 30P has an edge 30PE. Thereafter, the above-described anisotropic etching process sequence was performed on the remaining portions of the layer of sidewall spacer material 26 to thereby define a second sidewall spacer 26SN positioned on a second exposed portion of the sacrificial gate structure and on the fins 18N. As before, the over-etch process is performed for a sufficient duration such that the fins 18N are cleared of any spacer material, as shown in FIG. 1E (view Y-Y). The exposed portion of the gate cap layer 24 is also etched or “gouged” during the formation of the spacer 26SN, as reflected by the recessed surface 24L.
In forming the spacers 26SP and 26SN, it is very important that the masking layers 30N, 30P overlap to some degree. With reference to FIG. 1E (view X-X), the position of the edge 30NE of the first etch mask 30N is indicated by a dashed line. The amount of the overlap 38 is ideally very small, e.g., about 10-20 nm, but it must be sufficiently large to account for all potential misalignment errors. Without such an overlay 38, a portion of the gate cap layer 24 would be exposed to both of the etching processes performed to form the spacers 26SP and 26SN, which might consume the entire affected portion of the gate cap layer 24 thereby exposing a portion of the underlying sacrificial gate electrode 22. If the sacrificial gate electrode 22 were to be exposed, epi semiconductor material would also undesirably form on the gate electrode 22 as well during the process of forming epi material 32 on the fins 18N, as described more fully below.
FIG. 1F depicts the device after several process operations have been performed. First, the masking layer 30P was removed and an epi pre-clean process was performed on the fins 18N to insure that the fins 18N are cleared of all undesirable materials, e.g., oxide materials. After the pre-clean process was performed, an epi deposition process was performed to form a semiconductor material 42 on the fins 18N. Dashed lines 44 depict the outline of the original fins 18N. At the point of fabrication depicted in FIG. 1F, traditional manufacturing techniques may be performed to complete the manufacture of the device 10, e.g., removal of the sacrificial gate structure, formation of a replacement gate structure that contains one or more metal layers, the formation of various conductive contact structures to various regions of the device 10, etc.
One problem that results from the above process sequence is the formation of a relatively large “bump” 40, as shown in FIG. 1F. The bump 40 is typically comprised of layers of silicon nitride material, and it may have an overall height 40H of about 30-60 nm, but the total height may vary with the overlay of the two masks 30N, 30P. The presence of the bump 40 creates problems in subsequent processing operations. For example, it is very important that the uppermost surface or topography of the materials on the substrate be substantially flat or planar. Absent such planarity, errors can arise in patterning structures, such as gate electrodes, to the precise dimensions required to manufacture integrated circuit devices. Avoiding undesirable surface topography is even more important as device dimensions continue to shrink. Chemical mechanical polishing (CMP) is one technique that device manufacturers have employed for many years in an effort to achieve acceptable levels of planarity of the substrates as they are processed. However, the presence of the large bump 40 makes it difficult to achieve a substantially planar surface during a CMP process. More specifically, performing the CMP process for a sufficient duration to insure removal of the bump 40 may cause unwanted dishing in other areas of the substrate, or even exposure of other materials that were not intended to be exposed. If the bump 40 is not substantially removed, then its presence will be reflected in the subsequent removal of layers of material below the bump 40, thereby leading to problems in removing the dummy poly gate structure below the bump 40.
Another problem with the above-described process sequence is related to the very high aspect ratios that are inherent in any FinFET device. Typically, the gate structures of a FinFET device are relatively tall so that they may wrap around the fins and accommodate the use of self-aligned contacts. It is difficult to fully develop patterned photoresist masks in such a high topography environment. Additionally, the use of such under-developed photoresist masks during the etching processes that are performed to form the spacers 26SP and 26SN (which are typically made of silicon nitride), may lead to so-called “scumming”—a process whereby hydrogen outgassing from the underlying layer of silicon nitride results in photoresist material being left in undesirable areas. In general, scumming causes patterns not to etch correctly and may leave permanent parasitic spacers where the resist has polymerized. One other issue is that, as noted above, the fins must be cleared of the spacer material 26 prior to the formation of epi semiconductor material on the fins without an overconsumption of the fin material. One technique to insure this happens is to employ a relatively high oxygen flow rate during the over-etch process described above. Unfortunately, the high oxygen flow rate causes a greater consumption of the photoresist mask. Thus, the amount of over-etching that can be done (to insure the fins are cleared of silicon nitride material) is limited as it may consume too much of the photoresist mask. On the other hand, increasing the thickness of the photoresist mask to compensate for such consumption makes forming accurate photoresist masks more difficult in terms of precision of features and overlay accuracy. In short, the high aspect ratio associated with the formation of FinFET devices makes the above-described double-spacer, double-epi process flow very difficult.
The present disclosure is directed to various methods of forming FinFET devices with a shared gate structure that may solve or reduce one or more of the problems identified above.